1. Field of the Invention
This invention relates to a package for housing an electronic circuit. More particularly, the invention relates to an electronic package component formed from metal infiltrated graphite.
2. Description of Related Art
Microelectronic devices are typically manufactured from a semiconductor material such as silicon, germanium or gallium/arsenide. The semiconductor material is fashioned into a die, a generally rectangular structure having circuitry formed on one surface. Along the periphery of that surface are input/output pads to facilitate electrical interconnection to external components.
The semiconductor device is brittle and requires protection from moisture and mechanical damage. This protection is provided by an electronic package. The electronic package further contains an electrically conductive means to transport electrical signals between the semiconductor device and external circuitry.
One type of electronic package has separate base and cover components defining a cavity. A leadframe is disposed between the base and cover and bonded to both by a dielectric sealant. The inner lead ends of the leadframe extend into the cavity and are electrically interconnected to one or more semiconductor devices housed within that cavity. The exterior leads of the leadframe extend beyond the electronic package perimeter for electrical interconnection to external circuitry. Typical dielectric sealing means includes sealing glasses and polymer adhesives.
One or more semiconductor devices are bonded to the package base. In selecting a material for use as a package base, weight, coefficient of thermal conductivity, and coefficient of thermal expansion are considered. The electronic package is only one component on an electronic assembly, such as a printed circuit board, which is incorporated into a device such as a computer. The weight of the device is influenced by the weight of each component. It is desirable to minimize the weight of each electronic package.
When the semiconductor device is under power, the internal electrical resistivity of the device converts a portion of the electrical signals passing through the device to heat. It is necessary to remove the generated heat to maintain efficient operation of the semiconductor device. A primary means to remove the heat is conduction through the package base. It is desirable that the base have a high coefficient of thermal conduction.
A gallium/arsenide semiconductor device has a coefficient of thermal expansion of about 6.5.times.10.sup.-6 /.degree.C. The coefficient of thermal expansion of a silicon based device is about 3.0.times.10.sup.-6 /.degree.C. If the package base has a coefficient of thermal expansion close to that of the semiconductor device, mounting of the semiconductor device to the base is simplified. Any one of a number of solders, polymer adhesives, or sealing glasses may be utilized. When there is a significant variation in the coefficient of thermal expansion between the semiconductor device and the package base, the mismatch causes stresses which can fracture the device. Reducing the coefficient of thermal expansion mismatch reduces the stresses on the device. To compensate for a large mismatch, either compliant polymer adhesives or buffered die attach systems are required. The compensating die attach systems add cost and complexity to the electronic package. It is therefore desirable that the semiconductor package base have a coefficient of thermal expansion approximately equal to or at least somewhat close to that of the semiconductor device.
Adhesively sealed electronic packages having plastic, ceramic or metallic base components are disclosed in U.S. Pat. Nos. 4,105,861 to Hascoe, 4,521,469 to Butt and 4,939,316 to Mahulikar. Bases formed from copper or aluminum alloys satisfy two of the three requirements described above in that they are light weight and have high coefficients of thermal conductivity. The components also have a high coefficient of thermal expansion necessitating a compliant or buffered die attach system.
Composite base materials, such as copper/molybdenum or copper/tungsten are typically formed by infiltrating a porous molybdenum or tungsten substrate with molten copper or by powder metallurgy. The use of these composites in electronic packages is disclosed in U.S. Pat. Nos. 4,680,618 to Koroda and 5,111,277 to Medeiros, III. The composites have a coefficient of thermal expansion approximately equal to that of the semiconductor device and a high coefficient of thermal conductivity. The composite materials are much heavier than components formed from copper or aluminum alloys.
Another type of composite is disclosed in U.S. Pat. No. 4,761,518 to Butt. A mixture of ceramic, glass and metal particles are pressed and sintered into a composite. By careful selection of the composition and volume percent of each of the three elements, light weight composites with a high coefficient of thermal conductivity and coefficient of thermal expansion may be developed. These materials are relatively expensive to manufacture and may have property variations from part to part.
One light weight material with a high coefficient of thermally conductivity and a coefficient of thermal expansion close to that of a silicon based semiconductor device is graphite. Graphite has excellent machinability and is relatively low cost. However, graphite is porous, nonhermetic, brittle, low strength and easily eroded. For these reasons, graphite has not been exploited for electronic package components.
Graphite has been disclosed as the core for printed circuit boards in U.S. Pat. No. 4,963,414 to LeVasseur. Metallic layers are adhesively bonded to a graphite core. The metallic layers provide strength and environmental protection to the planar faces of the graphite core. However, the edges of the graphite are exposed to the environment and subject to mechanical or chemical erosion. Further, the adhesive layer between the metallic layers and the graphite core electrically isolates the metallic layer from the graphite core and slightly increases the thermal resistance between a semiconductor device mounted on the metallic layer and the graphite core.